Introduction

With the nearing end of Moore’s Law, domain-specific hardware and architectures are growing rapidly. The notion of performing some tasks more efficiently (area, speed and/or energy) rather than improving performance for general purpose computing has led to the proliferation of special-purpose accelerators. With their widespread use, hard optimization problems have been a primary target of this approach and a variety of different domain-specific hardware architectures have emerged (see, Ref. [1] for a general and recent review). As an example of this growing trend, probabilistic bits or p-bits were introduced [2] as a building block which can accelerate a broad family of algorithms including Monte Carlo, Markov Chain Monte Carlo [3], Quantum Monte Carlo, statistical sampling for Bayesian inference and Boltzmann
machine learning [4] methods. p-bits have been shown to be compatible with powerful optimization techniques such asparallel tempering [5] with competitive performance relative to all other Ising machines (classical and quantum) in select problems such as integer factorization and Boolean satisfiability [6]. Their combination with sophisticated algorithms [7] could yield further advantages. A natural advantage of the p-bit model is its native mapping to the Ising model and to the natural generalization of Ising Models. This ensures that coupled p-bits can systematically probe the exact Boltzmann distribution through Gibbs or Metropolis sampling without any approximations or reductions,
often necessary in alternative, non-bistable abstractions of the Ising spin. One particularly promising small-scale demonstration of p-bits in an asynchronously operating mode was performed in Ref. [8]. Combined with key breakthrough experiments demonstrating nanosecond fluctuations in suitably designed low barrier magnetic tunnel junctions (MTJ) [9], [10], these results suggest the intriguing possibility of designing > million bit probabilistic computers [11] in light of the remarkable advances in the magnetic memory chip industry reaching gigabit densities [12], [13]. Even though large scale p-bit emulators have been designed and tested in FPGAs or ASICs, [3], [6], [11], [14], [15], virtually all of these implementations have been on synchronous hardware where a global clock controlled the information flow. In this paper, we make a first attempt in designing and building a physics-inspired, truly asynchronous architecture, closely emulating the dynamics of interacting nanodevicebased p-bits. This physics-inspired architecture bears similarities to locally interacting (sparsely connected) and asynchronous bodies with probabilistic dynamics (FIG. 1, upper panel). We achieve the design by an unconventional use of FPGAs where individual p-bits are activated by decoupled ring oscillators and can have overlapping and out-of-phase clocks with different frequencies. Considering how variations may influence individual p-bit behavior in magnetic tunnel junction based designs [16] the behavior of asynchronous p-computers with built-in variations is worth investigating. To compare the performance of the truly asynchronous computer in the FPGA, we choose the planted Ising model where a hard optimization problem is generated with a planted solution [17], [18], allowing a reliable evaluation of the asynchronous design with respect to exact Gibbs sampling.